Features: · Serial or parallel expansion without extra gating· Magnitude comparison of any binary words· Output capability: standard· ICC category: MSIPinoutDescriptionThe 74HCT85 is high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in c...
74HCT85: Features: · Serial or parallel expansion without extra gating· Magnitude comparison of any binary words· Output capability: standard· ICC category: MSIPinoutDescriptionThe 74HCT85 is high-speed Si-g...
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Features: · Output capability: standard· ICC category: SSIPinoutDescription The 74HC/HCT02 are hig...
Features: · Level shift capability· Output capability: standard (open drain)· ICC category: SSIPin...
The 74HCT85 is high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HCT85 is 4-bit magnitude comparators that can be expanded to almost any length. They perform comparison of two 4-bit binary, BCD or other monotonic codes and present the three possible magnitude results at the outputs (QA>B, QA=B and QA<B). The 4-bit inputs are weighted (A0 to A3 and B0 to B3), where A3 and B3 are the most significant bits.
The operation of the "85" is described in the function table, showing all possible logic conditions. The upper part of the table describes the normal operation under all conditions that will occur in a single device or in a series expansion scheme. In the upper part of the table the three outputs are
mutually exclusive. In the lower part of the table, the outputs reflect the feed forward conditions that exist in the parallel expansion scheme.
For proper compare operation the expander inputs (IA>B, IA=B and IA<B) to the least significant position must be connected as follows: IA<B = IA>B = = LOW and IA=B = HIGH.
For words greater than 4-bits, units can be cascaded by connecting outputs QA<B, QA>B and QA=B to the corresponding inputs of the significant comparator.
The 74HCT85 is designed as high-speed si-gate CMOS devices and are pin compatible with low power schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. It is 4-bit magnitude comparators that can be expanded to almost any length. They perform comparison of two 4-bit binary, BCD or other monotonic codes and present the three possible magnitude results at the outputs (Qa>b, Qa=b and Qa<b). The 4-bit inputs are weighted (A0 to A3 and B0 to B3), where A3 and B3 are the most significant bits.
The four features of the 74HCT85. The first one is serial or parallel expansion without extra gating. The second one is magnitude comparison of any binary words. The third one is its output capability is standard. The fourth one is its ICC category is MSI. That are all the main features.
Some important AC characteristics and transfer characteristics of the 74HCT85 have been concluded into several points as follow.For Tamb=25°C the first one is about its propagation delay An, Bn to Qa>b or Qa<b which would be typ 63ns and max 195ns at Vcc=2.0V and would be typ 23ns and max 39ns at Vcc=4.5V and would be typ 18ns and max 33ns at Vcc=6.0V. The second one is about its propagation delay An, Bn to Qa=b which would be typ 58ns and max 175ns at Vcc=2.0V and typ 21ns and max 35ns at Vcc=4.5V and would be typ 17ns and max 30ns at Vcc=6.0V. The third one is about its propagation delay Ia<b, Ia=b, Ia>b to Qa<b, Qa>b which would be typ 50ns and max 140ns at Vcc=2.0V and typ 18ns and max 28ns at Vcc=4.5V and would be typ 14ns and max 24ns at Vcc=6.0V. The fourth one is about its propagation delay Ia=b to Qa=b which would be typ 39ns and max 120ns at Vcc=2.0V and typ 14ns and max 24ns at Vcc=4.5V and would be typ 11ns and max 20ns at Vcc=6.0V. And so on. The fifth one is about its output transition time which would be typ 19ns and max 75ns at Vcc=2.0V and typ 7ns and max 15ns at Vcc=4.5V and would be typ 6ns and max 13ns at Vcc=6.0V. And so on. For more information about the 74HCT85 please contact us for details.