74HCT75

The 74HCT75 is high-speed Si-gate CMOS devices nd are pin compatible with low power Schottky TTL LSTTL). They are specified in compliance with JEDEC tandard no. 7A.

The 74HCT75 has four bistable latches. The two atches are simultaneously controlled by one of two active IGH enable inputs (LE_1-2 and LE_3-4). When LE_n-n is IGH, the data enters the latches and appears at the nQ utputs. The nQ outputs follow the data inputs (nD) as long s LE_n-n is HIGH (transparent). The data on the nD inputs ne set-up time prior to the HIGH-to-LOW transition of the E_n-n will be stored in the latches. The latched outputs emain stable as long as the LE_n-n is LOW.