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74HCT74

Features: · Wide supply voltage range from 2.0 to 6.0 V· Symmetrical output impedance· High noise immunity· Low power dissipation· Balanced propagation delays· ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V.PinoutSpecifications SYMBOL PARAMETER CONDI...

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SeekIC No. : 004250950 Detail

74HCT74: Features: · Wide supply voltage range from 2.0 to 6.0 V· Symmetrical output impedance· High noise immunity· Low power dissipation· Balanced propagation delays· ESD protection: HBM EIA/JESD22-A114-A ...

74HCT74 Data Sheet

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Part Number:
74HCT74
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/25

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Product Details

Description



Features:

· Wide supply voltage range from 2.0 to 6.0 V
· Symmetrical output impedance
· High noise immunity
· Low power dissipation
· Balanced propagation delays
· ESD protection:
    HBM EIA/JESD22-A114-A exceeds 2000 V
    MM EIA/JESD22-A115-A exceeds 200 V.


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage   -0.5 +7.0 V
IIK input diode current VI < -0.5 V or VI > VCC + 0.5 V;note 1 - ±20 mA
IOK output diode current VO < -0.5 V or VO > VCC + 0.5 V;note 1 - ±20 mA
IO output source or sink current -0.5 V < VO < VCC + 0.5 V; note 1 - ±25 mA
ICC, IGND VCC or GND current   - ±100 mA
Tstg storage temperature   -65 +150
Ptot power dissipation Tamb = -40 to +125 ; note 2 - 500 mW



Description

The 74HCT74 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HCT74 is dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs.

The set and reset of the 74HCT74 are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt-trigger action of the 74HCT74 in the clock input makes the circuit highly tolerant to slower clock rise and fall times.




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