74HCT7273

Note
1.For DIP package: above 70°C the value of P_Dderates linearly with 12mW/K.
2.For SO package: above 70°C the value of P_Dderates linearly with 8mW/K.

The 74HCT7273 is a high-speed SI-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard no 7A.

The 74HCT7273 has eight edge-triggered D-type flip-flops with individual Dinputs and Q outputs. The common Clock (CP) and Master Reset (,MR) inputs load and reset (clear) all flip-flops simultaneously.

The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.

A LOW level on the ,MR input forces all outputs LOW, independently of the clock or data inputs.

The 74HCT7273 is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements.

The 74HCT7273 has open-drain N-outputs, which are clamped by a diode connected to V_CC. When a HIGH is clocked in the flip-flop, the output comes in the high-impedance OFF-state. The output may now be pulled to any voltage between GND and VOmax. This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and OR-tied output applications, the device must have a pull-up resistor to establish a logic HIGH level.