74HCT652

The 74HCT652 is high-speed SI-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified incompliance with Jedec standard no. 7A.

The 74HCT652 consist of 8 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and central circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the "A" or "B" or both buses, will be stored in the internal registers, at the appropriate clock pins (CP_AB or CP_BA) regardless of the select pins (S_AB and S_BA) or output enable (OE_AB and OE_BA) control pins. Depending on the select inputs S_AB and S_BA data can directly go from input to output (real time mode) or data can be controlled by the clock (storage mode), this is when the output enable pins this operating mode permits. The output enable pins OE_AB and OE_BA of the 74HCT652 determine the operation mode of the transceiver. When OE_AB is LOW, no data transmission from An to Bn ispossible and when OE_BA is HIGH, there is no data transmission from Bn to An possible. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OE_AB and OE_BA. In this configuration each output reinforces its input. Thus when all other data sources to the two sets of bus lines are at high-impedance, each set of the bus lines will remain at its last state. This type differs from the HC/HCT646 in one extra bus-management function. This is the possibility to transfer stored "A data to the "B" bus and transfer stored "B" data to the "A" bus at the same time. The examples at the application information demonstrate all bus management functions. Schmitt-trigger action of the 74HCT652 in the clock inputs makes the circuit highly tolerant to slower clock rise and fall times.