74HCT4353

The 74HCT4353 is high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A.

The 74HCT4353 is triple 2-channel analog multiplexers/demultiplexers with two common enable inputs (E₁ and E₂) and a latch enable input (LE). Eachmultiplexer has two independent inputs/outputs (nY₀ and nY₁), a common input/output (nZ) and select inputs (S₁ to S₃).

Each multiplexer/demultiplexer of the 74HCT4353 contains two bidirectional analog switches, each with one side connected to an independent input/output (nY₀ and nY₁) and the other side connected to a common input/output (nZ).

With E₁ LOW and E₂ HIGH, one of the two switches is selected (low impedance ON-state) by S₁ to S₃. The data at the select inputs may be latched by using the active LOW latch enable input (LE). When LE is HIGH, the latch is transparent. When either of the two enable inputs, E₁ (active LOW) and E₂ (active HIGH), is inactive, all analog switches are turned off.

V_CC and GND are the supply voltage pins for the digital control inputs (S₁ to S₃, LE, andE₂). The V_CC to GND ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT. The analog inputs/outputs (nY₀ and nY₁, and nZ) can swing between V_CC as a positive limit and V_EE as a negative limit. V_CC - V_EE may not exceed 10.0 V.

For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground).