74HCT4015

The 74HCT4015 is high-speed Si-gate CMOS devices and are pin compatible with the "4015" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A.

The 74HCT4015 is dual edge-triggered 4-bit static shift registers (serial-to-parallel converters). Each shift register has a serial data input (1D and 2D), a clock input (1CP and 2CP), four fully buffered parallel outputs (1Q₀ to 1Q₃ and 2Q₀ to 2Q₃) and an overriding asynchronous master reset (1MR and 2MR). Information of the 74HCT4015 present on nD is shifted to the first register position, and all data in the register is shifted one position to the right on the LOW-to-HIGH transition of nCP.

A HIGH on nMR clears the register and forces nQ₀ to nQ₃ to LOW, independent of nCP and nD.