74HCT390

The 74HCT390 is high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HCT390 is dual 4-bit decade ripple counters divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections are normally used in a BCD decade or bi-quinary configuration, since they share a common master reset input (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clocks (nCP₀ and nCP₁ ) of each section allow ripple counter or frequency division applications of divide-by-2, 4, 5, 10, 20, 25, 50 or 100.

Each section of the 74HCT390 is triggered by the HIGH-to-LOW transition of the clock inputs (nCP₀ and nCP₁ ). For BCD decade operation, the nQ₀ output is connected to the nCP₁ input of, the divide-by-5 section. For bi-quinary decade operation, the nQ₃ output is connected to the nCP₀ input and nQ₀ becomes the decade output.

The master reset inputs (1MR and 2MR) of the 74HCT390 are active HIGH asynchronous inputs to each decade counter which operates on the portion of the counter identified by the "1" and "2" prefixes in the pin configuration. A HIGH level on the nMR input overrides the clocks and sets the four outputs LOW