74HCT165

The 74HCT165 is high-speed Si-gate CMOS devicesand are pin compatible with low power Schottky TTL(LSTTL). They are specified in compliance with JEDECstandard no. 7A.
The 74HCT165 is 8-bit parallel-load or serial-in shiftregisters with complementary serial outputs (Q₇ andQ₇)available from the last stage. When the parallel load(PL) input is LOW, parallel data from the D0 toD7 inputs are loaded into the register asynchronously.
When PL is HIGH, data enters the register serially at theDs input and shifts one place to the right(Q0 Q1 Q2,etc.) with each positive-going clocktransition. This feature allows parallel-to-serial converterexpansion by tying the Q7 output to the DS input of thesucceeding stage.
The clock input of the 74HCT165 is a gated-OR structure which allows oneinput to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitraryand can be reversed for layout convenience. TheLOW-to-HIGH transition of inputCE should only takeplace while CP HIGH for predictable operation. Either theCP or the CE should be HIGH before theLOW-to-HIGH transition of PLto prevent shifting the datawhen PL is activated.