74HCT137

The 74HCT137 is high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HCT137 is 3-to-8 line decoder/demultiplexers with latches at the three address inputs (An). The "137" essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the "137" acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH.

The output enable input (E₁ and E₂) of the 74HCT137 controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E₁ is LOW and E₂ is HIGH.


The "137" is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus oriented systems.