74HCT107

The 74HCT107 is high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HCT107 is dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.

The J and K inputs of the 74HCT107 must be stable one set-up time prior the HIGH-to-LOW clock transition for predictable operation.

The reset (nR) of the 74HCT107 is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.