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74HC73

Features: · Low-power dissipation· Complies with JEDEC standard no. 7A·ESD protection: HBM EIA/JESD22-A114-B exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V.·Multiple package options·Specified from -40 °C to +80 °C and from -40 °C to +125 °C.PinoutSpecifications SYMBOL PARAMETER CONDITION...

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SeekIC No. : 004250794 Detail

74HC73: Features: · Low-power dissipation· Complies with JEDEC standard no. 7A·ESD protection: HBM EIA/JESD22-A114-B exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V.·Multiple package options·Specified fro...

74HC73 Data Sheet

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Part Number:
74HC73
Supply Ability:
5000

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  • 1~5000
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Product Details

Description



Features:

· Low-power dissipation
· Complies with JEDEC standard no. 7A
·ESD protection:
    HBM EIA/JESD22-A114-B exceeds 2000 V
    MM EIA/JESD22-A115-A exceeds 200 V.
·Multiple package options
·Specified from -40 °C to +80 °C and from -40 °C to +125 °C.


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage   -0.5 +7.0 V
IIK input diode current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA
IOK output diode current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA
IO output source or sink current VO = -0.5 V to VCC + 0.5 V - ±25 mA
ICC VCC or GND current   - ±50 mA
Tstg storage temperature   -65 +150 °C
Ptot
 power dissipation        
DIP16 package   [1] - 750 mW
SO16 and SSOP16
packages		   [2] - 500 mW

[1] Above 70 °C: Ptot derates linearly with 12 mW/K.
[2] Above 70 °C: Ptot derates linearly with 8 mW/K.


Description

The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A.

The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary nQ and nQ outputs.

The J and K inputs of the 74HC73 must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.

The reset (nR) of the 74HC73 is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.




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