74HC563

Features:

HIGH SPEED
tPD = 13 ns (TYP.) AT VCC = 5 V LOWPOWER DISSIPATION
ICC = 4 mA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE
IOL = zIOHz= 6 mA (MIN.) BALANCEDPROPAGATION DELAYS
tPLH = tPHL WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS563/573



Pinout




Specifications

Symbol	Parameter	Value	Unit
VCC	Supply Voltage	-0.5 to +7	V
VI	DC Input Voltage	-0.5 to VCC + 0.5	V
VO	DC Output Voltage	-0.5 to VCC + 0.5	V
IIK	DC Input Diode Current	± 20	mA
IOK	DC Output Diode Current	± 20	mA
IO	DC Output Source Sink Current Per Output Pin	± 35	mA
ICC or IGND	DC VCC or Ground Current	± 70	mA
PD	Power Dissipation	500 (*)	mW
Tstg	Storage Temperature	-65 to +150	o C
TL	Lead Temperature (10 sec)	300	o C

Description

The M54/74HC563 is high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C2MOS technology.

These ICs of the 74HC563 archive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation.

These 8 bit D-Type latches of the 74HC563 are controlled by a latch enable input (LE) and a output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while high level the outpts will be in a high impedance state.

The application designer of the 74HC563 has a choise of combination of inverting and non inverting outputs.

The three state output configuration and the wide choise of outline make bus organized system simple.

All inputs are equipped of the 74HC563 with protection circuits against discharge and transient excess voltage.