74HC4520

The 74HC4520 is high-speed Si-gate CMOS devices and are pin compatible with the "4520" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A.

The 74HC4520 is dual 4-bit internally synchronous binary counters with an active HIGH clock input (nCP₀) and an active LOW clock input (nCP₁), buffered outputs from all four bit positions (nQ₀ to nQ₃) and an active HIGH overriding asynchronous master reset input (nMR).

The counter of the 74HC4520 advances on either the LOW-to-HIGH transition of nCP0 if nCP₁ is HIGH or the HIGH-to-LOW transition of nCP1 if nCP₀ is LOW. Either nCP₀ or nCP₁ may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ₀ to nQ₃ = LOW) independent of nCP₀ and nCP₁.