74HC4040

Features: Multiple package optionsComplies with JEDEC standard no. 7AESD protection: HBM JESD22-A114-C exceeds 2000 VMM JESD22-A115-A exceeds 200 VSpecified from -40 °C to +85 °C and from -40 °C to +125 °CApplicationFrequency dividing circuitsTime delay circuitsControl countersSpecifications ...

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74HC4040 Picture
SeekIC No. : 004250763 Detail

74HC4040: Features: Multiple package optionsComplies with JEDEC standard no. 7AESD protection: HBM JESD22-A114-C exceeds 2000 VMM JESD22-A115-A exceeds 200 VSpecified from -40 °C to +85 °C and from -40 °C to ...

floor Price/Ceiling Price

Part Number:
74HC4040
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/25

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Product Details

Description



Features:

Multiple package options
Complies with JEDEC standard no. 7A
ESD protection:
   HBM  JESD22-A114-C exceeds 2000 V
   MM  JESD22-A115-A exceeds 200 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C



Application

Frequency dividing circuits
Time delay circuits
Control counters



Specifications

Symbol Parameter Conditions Min Max Unit
VCC supply voltage   -0.5 +7 V
IIK input diode current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA
IOK output diode current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA
IO output source or sink current -0.5 V < VO < VCC + 0.5 V - ±25 mA
ICC quiescent supply current   - ±50 mA
IGND ground current   - ±50 mA
Tstg storage temperature   -65 +150 °C
Ptot power dissipation Tamb = -40 °C to +125 °C [1]    
  DIP16 package   - 750 mW
  SO16, SSOP16, TSSOP16 and
DHVQFN16 packages
  - 500 mW



Description

The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin ompatible with the HEF4040B series. They are specified in compliance with JEDEC tandard no. 7A.

The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), n overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to 11). The counter advances on the HIGH-to-LOW transition of CP.

A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP.

Each counter stage of the 74HC4040 is a static toggle flip-flop.




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