Features: Multiple package optionsComplies with JEDEC standard no. 7AESD protection: HBM JESD22-A114-C exceeds 2000 VMM JESD22-A115-A exceeds 200 VSpecified from -40 °C to +85 °C and from -40 °C to +125 °CApplicationFrequency dividing circuitsTime delay circuitsControl countersSpecifications ...
74HC4040: Features: Multiple package optionsComplies with JEDEC standard no. 7AESD protection: HBM JESD22-A114-C exceeds 2000 VMM JESD22-A115-A exceeds 200 VSpecified from -40 °C to +85 °C and from -40 °C to ...
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Features: · Output capability: standard· ICC category: SSIPinoutDescription The 74HC/HCT02 are hig...
Features: · Level shift capability· Output capability: standard (open drain)· ICC category: SSIPin...
Symbol | Parameter | Conditions | Min | Max | Unit |
VCC | supply voltage | -0.5 | +7 | V | |
IIK | input diode current | VI < -0.5 V or VI > VCC + 0.5 V | - | ±20 | mA |
IOK | output diode current | VI < -0.5 V or VI > VCC + 0.5 V | - | ±20 | mA |
IO | output source or sink current | -0.5 V < VO < VCC + 0.5 V | - | ±25 | mA |
ICC | quiescent supply current | - | ±50 | mA | |
IGND | ground current | - | ±50 | mA | |
Tstg | storage temperature | -65 | +150 | °C | |
Ptot | power dissipation | Tamb = -40 °C to +125 °C | [1] | ||
DIP16 package | - | 750 | mW | ||
SO16, SSOP16, TSSOP16 and DHVQFN16 packages |
- | 500 | mW |
The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin ompatible with the HEF4040B series. They are specified in compliance with JEDEC tandard no. 7A.
The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), n overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to 11). The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP.
Each counter stage of the 74HC4040 is a static toggle flip-flop.