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74HC3G07

Features: • Wide supply voltage range from 2.0 to 6.0 V• High noise immunity• Low power dissipation• ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V.• Multiple package options• Specified from −40 to +85 and −40...

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SeekIC No. : 004250756 Detail

74HC3G07: Features: • Wide supply voltage range from 2.0 to 6.0 V• High noise immunity• Low power dissipation• ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A...

74HC3G07 Data Sheet

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Part Number:
74HC3G07
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

• Wide supply voltage range from 2.0 to 6.0 V
• High noise immunity
• Low power dissipation
• ESD protection:
   HBM EIA/JESD22-A114-A exceeds 2000 V
   MM EIA/JESD22-A115-A exceeds 200 V.
• Multiple package options
• Specified from −40 to +85 and −40 to +125.


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage   −0.5 +7.0 V
IIK input diode current VI < −0.5 V or VI >VCC + 0.5 V − ±20 mA
IOK output diode current VO < −0.5 V − -20 mA
VO output voltage active mode; note 1 −0.5 VCC + 0.5 V
high-impedance mode; note 1 −0.5 7.0 V
IO output source or sink current −0.5 V < VO < 7.0 V − -25 mA
ICC VCC or GND current note 1 − 50 mA
Tstg storage temperature   −65 +150
PD power dissipation Tamb = −40 to +125 ; note 2 − 300 mW

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. Above 110 the value of PD derates linearly with 8 mW/K.


Description

The 74HC3G07 is a high-speed Si-gate CMOS device. Specified in compliance with JEDEC standard no. 7A.

The 74HC3G07 provides three non-inverting buffers.

The outputs of the 74HC3G07 devices are open drains and can be connected to other open-drain outputs to implement active-LOW, wired-OR or active-HIGH wired-AND functions. For digital operation this devicemust have a pull-up resistor to establish a logic HIGH-level.




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