74HC195

The 74HC195 is high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC195 performs serial, parallel, serial-to-parallel or parallel-to-serial data transfer at very high speeds. The "195" operates on two primary modes:shift right (Q_oQ₁) and parallel load, which are controlled by the state of the parallel load enable (PE) input. Serial data enters the first flip-flop (Q₀) via the J and K inputs when the PE input is HIGH and shifted one bit in the direction Q₀Q₁ Q₂  Q₃ following each LOW-to-HIGH clock transition. The J and K inputs provide the flexibility of the JK type input of the 74HC195 for special applications and by tying the pins together, the simple D-type input for general applications. The "195" appears as four common clocked D flip-flops when the PE input is LOW.

After the LOW-to-HIGH clock transition, data on the parallel inputs (D₀ to D₃) is transferred to the respective Q₀ to Q₃ outputs. Shift left operation (Q₃  Q₂) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input LOW.

All parallel and serial data transfers of the 74HC195 are synchronous, occurring after each LOW-to-HIGH clock transition. There is no restriction on the activity of the J, K, Dn and PE inputs for logic operation other than the set-up and hold time requirements. A LOW on the asynchronous master reset (MR) input sets all Q outputs LOW, independent of any other input condition.