74FCT646CT

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.

The 74FCT646CT consists of a bus transceiver with 3-state D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The FCT646T utilizes the enable control (G) and direction (DIR) pins to control the transceiver functions.

SAB and SBA control pins of the 74FCT646CT are provided to select either real- time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input level selects real-time data and a high selects stored data.

Data of the 74FCT646CT on the A or B data bus, or both, can be stored in the internal D flipflops by low-to-high transitions at the appropriate clock pins (CPAB or CPBA), regardless of the select or enable control pins.