Features: •Std., A, and C grades•Low input and output leakage 1A (max.)•CMOS power levels•True TTL input and output compatibility: VOH = 3.3V (typ.) VOL = 0.3V (typ.)•High Drive outputs (-15mA IOH, 48mA IOL)•Meets or exceeds JEDEC standard 18 specifications̶...
74FCT573T: Features: •Std., A, and C grades•Low input and output leakage 1A (max.)•CMOS power levels•True TTL input and output compatibility: VOH = 3.3V (typ.) VOL = 0.3V (typ.)•H...
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Features: Std., A and C speed gradesLow input and output leakage ?1A (max.)CMOS power levelsTrue T...
Features: Std., A and C speed gradesLow input and output leakage ?1A (max.)CMOS power levelsTrue T...
•Std., A, and C grades
•Low input and output leakage 1A (max.)
•CMOS power levels
•True TTL input and output compatibility: VOH = 3.3V (typ.) VOL = 0.3V (typ.)
•High Drive outputs (-15mA IOH, 48mA IOL)
•Meets or exceeds JEDEC standard 18 specifications
•Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked)
•Power off disable outputs permit "live insertion"
•Available in the following packages: Industrial: SOIC, SSOP, QSOP, TSSOP Military: CERDIP, LCC
Symbol | Description | Max | Unit |
VTERM(2) | Terminal Voltage with Respect to GND | 0.5 to +7 | V |
VTERM(3) | Terminal Voltage with Respect to GND | 0.5 to VCC+0.5 | V |
TSTG | Storage Temperature | 65 to +150 | |
IOUT | DC Output Current | 60 to +120 | mA |
The 74FCT573T is an octal transparent latch built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is high. When LE of the 74FCT573T is low, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is low. When OE is high, the bus output is in the high-impedance state.