Features: • Std., A, and C grades• Low input and output leakage 1µA (max.)• CMOS power levels• True TTL input and output compatibility: VOH = 3.3V (typ.) VOL = 0.3V (typ.)• High Drive outputs (-15mA IOH, 48mA IOL)• Meets or exceeds JEDEC standard 18 specif...
74FCT573AT: Features: • Std., A, and C grades• Low input and output leakage 1µA (max.)• CMOS power levels• True TTL input and output compatibility: VOH = 3.3V (typ.) VOL = 0.3V (ty...
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Features: Std., A and C speed gradesLow input and output leakage ?1A (max.)CMOS power levelsTrue T...
Features: Std., A and C speed gradesLow input and output leakage ?1A (max.)CMOS power levelsTrue T...
Symbol |
Description |
Max |
Unit |
VTERM(2) |
Terminal Voltage with Respect to GND |
0.5 to +7 |
V |
VTERM(3) |
Terminal Voltage with Respect to GND |
0.5 to VCC+0.5 |
V |
TSTG |
Storage Temperature |
65 to +150 |
°C |
IOUT |
DC Output Current |
60 to +120 |
mA |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
The 74FCT573AT is an octal transparent latch built using an advanced dualmetal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is high. When LE is low, the data that meetsthe set-up time is latched. Data appears on the bus when the Output Enable (OE) is low. When OE of the 74FCT573AT is high, the bus output is in the high-impedance state.