74FCT273A

Features: •IDT54/74FCT273 equivalent to FASTM speed;•IDT54/74FCT273A 45% faster than FAST•IDT54/74FCT273C 55% faster than FAST•Equivalent to FAST output drive over full temperature and voltage supply extremes•IOL = 48mA (commercial) and 32mA (military)•CMOS powe...

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SeekIC No. : 004250244 Detail

74FCT273A: Features: •IDT54/74FCT273 equivalent to FASTM speed;•IDT54/74FCT273A 45% faster than FAST•IDT54/74FCT273C 55% faster than FAST•Equivalent to FAST output drive over full tempe...

floor Price/Ceiling Price

Part Number:
74FCT273A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

•IDT54/74FCT273 equivalent to FASTM speed;
•IDT54/74FCT273A 45% faster than FAST
•IDT54/74FCT273C 55% faster than FAST
•Equivalent to FAST output drive over full temperature and voltage supply extremes
•IOL = 48mA (commercial) and 32mA (military)
•CMOS power levels (1mW typ. static)
•TTL input and output level compatible
•CMOS output level compatible
•Substantially lower input current levels than FAST (5A max.)
•Octal D flip-flop with Master Reset
•JEDEC standard pinout for DIP and LCC
•Product available in Radiation Tolerant and Radiation Enhanced versions
•Military product compliant to MIL-STD-883, Class B




Pinout

  Connection Diagram


Specifications

Symbol Rating Commercial Military Unit
VTER(2) Terminal Voltagewith Respectto GND 0.5 to +7.0 0.5 to +7.0 V
VTER(3) Terminal Voltagewith Respectto GND 0.5 to VCC 0.5 to VCC V
TA OperatingTemperature 0 to +70 55 to +125
TBIAS TemperatureUnder Bias 55 to +125 65 to +135
TSTG StorageTemperature 55 to +125 65 to +150
PT Power Dissipation 0.5 0.5 W
IOUT DC Output Current 120 120 mA



Description

The 74FCT273A is octal D flip-flops built using an advanced dual metal CMOS technology. The IDT54/ 74FCT273/A/C have eight edge-triggered D-type flip-flops with individual D inputs and O outputs. The common buffered Clock (CP) and Master Reset (MR ) inputs load and reset (clear) all flip-flops simultaneously.

The register of the 74FCT273A is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's O output.

All outputs of the 74FCT273A will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR  input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.




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