Features: 0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage `1`A (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,15.7 mil pitch TVSOP and 25 mil pitch Cerpack
Extended commercial range of -40`C to +85`C
VCC = 5V `10%
Balanced Output Drivers: `24mA (commercial), `16mA (military)
Reduced system switching noise
Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,TA = 25`C
Specifications
|
Symbol |
Description |
Max. |
Unit |
|
VTERM(2) |
Terminal Voltage with Respect to
GND |
0.5 to +7.0 |
V |
|
VTERM(3) |
Terminal Voltage with Respect to
GND |
0.5 to
VCC +0.5 |
V |
|
TSTG |
Storage Temperature |
65 to +150 |
`C |
|
IOUT |
DC Output Current |
60 to +120 |
mA |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
DescriptionThe 74FCT162652T 16-bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power devices are organized as two independent 8-bit bus transceivers with 3-state D-type registers. For example, the xOEAB and xOEBA signals control the transceiver functions.
The xSAB and xSBA control pins of the 74FCT162652T are provided to select either real time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real time data. A LOW input level selects real-time data and a HIGH level selects stored data.
Data on the A or B data bus, or both, can be stored in the internal D-flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (xCLKAB or xCLKBA), regardless of the select or enable control pins. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin.
The 74FCT162652T are ideally suited for driving high capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.
The 74FCT162652T have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall timesreducing the need for external series terminating resistors. The FCT162652T/AT/CT/ET are plug-in replacements for the FCT16652T/AT/CT/ET and ABT16652 for on-board bus interface applications.
74FCT162652T Data Sheet
