74FCT162511CT

The 74FCT162511CT 16-bit registered/latched transceiver with parity is built using advanced dual metal CMOS technology. This high-speed, low-power transceiver combines Dtype latches and D-type flip-flops to allow data flow in transparent, latched or clocked modes. The device has a parity generator/cheker in the A-to-B direction and a parity checker in the B-to-A direction. Error checking is done at the byte level with separate parity bits for each byte. Separate error flags exits for each direction with a single error flag indicating an error for either byte in the A-to-B direction and a second error flag indicating an error for either byte in the B-to-A direction. The parity error flags of the 74FCT162511CT are open drain outputs which can be tied together and/or tied with flags from other devices to form a single error flag or interrupt. The parity error flags are enabled by the OExx control pins allowing the designer to disable the error flag during combinational transitions.

The control pins LEAB, CLKAB and OEAB control operation of the 74FCT162511CT in the A-to-B direction while LEBA, CLKBA and OEBA control the B-to-A direction. GEN/CHK is only for the selection of A-to-B operation, the B-to-A direction is always in checking mode. The ODD/EVEN select is common between the two directions. Except for the ODD/EVEN control, independent operation can be achieved between the two directions by using the corresponding control lines.