74F825

Features: • High speed parallel registers with positive edge-triggered D-type flip-flops• High performance bus interface buffering for wide data/address paths or busses carrying parity• High impedance PNP base inputs for reduced loading (20mA in high and low states)• IIL is...

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SeekIC No. : 004249864 Detail

74F825: Features: • High speed parallel registers with positive edge-triggered D-type flip-flops• High performance bus interface buffering for wide data/address paths or busses carrying parity&#...

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Part Number:
74F825
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

• High speed parallel registers with positive edge-triggered D-type flip-flops
• High performance bus interface buffering for wide data/address paths or busses carrying parity
• High impedance PNP base inputs for reduced loading (20mA in high and low states)
• IIL is 20mA vs 1000mA for AM29821 series
• Buffered control inputs to reduce AC effects
• Ideal where high speed, light loading, or increased fan-in as required with MOS microprocessor
• Positive and negative over-shoots are clamped to ground
• 3-State outputs glitch free during power-up and power-down
• Slim Dip 300 mil package
• Broadside pinout compatible with AMD AM 29821-29826 series
• Outputs sink 64mA and source 24mA
• Industrial temperature range available (40°C to +85°C) for 74F823



Pinout

  Connection Diagram




Specifications

SYMBOL PARAMETER RATING UNIT
VCC Supply voltage 0.5 to +7.0 V
VIN Input voltage 0.5 to +7.0 V
IIN Input current 30 to +5 mA
VOUT Voltage applied to output in high output state 0.5 to VCC V
IOUT Current applied to output in low output state 128 mA
Tamb Operating free air temperature range Commercial range 0 to +70
Industrial range 40 to +85
Tstg Storage temperature range 65 to +150



Description

The 74F825 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity.

The 74F825 are buffered 10-bit wide versions of the popular 74F374/74F534 functions.

The 74F825 is the inverted output version of 74F821. The 74F823 and 74F824 are 9-bit wide buffered registers with clock enable (CE ) and master reset (MR) which are ideal for parity bus interfacing in high microprogrammed systems.

The 74F825 is the inverted version of 74F823.

The 74F825 are 8-bit buffered registers with all the 74F823/74F824 controls plus output enable (OE0, OE1, OE2) to allow multiuser control of the interface, e.g., CS, DMA, and RD/WR.

They are ideal for uses as an output port requiring high IOL/IOH.

The 74F825 is the inverted version of 74F825.


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