74F807

    The 74F807 is a registered transceiver that also has the capability to perform count, shift, and add functions. It is also has the capability to generate a parity bit output. All of this is done within a 28-pin package.

    The MR input of the 74F807 is an overriding asynchronous reset which forces the STATOUT output low as well as the A and B busses.

    The A and B busses of the 74F807 have separate OE inputs (OEA, OEB]. These inputs have no bearing on the internal functioning of this device only on the output states. Both OE pins are enabled low.

    All operating modes of the 74F807, other than clear,3-State, and the two hold modes require the rising edge of the clock. All setup and hold times must be observed for proper functioning.

    Data of the 74F807 on the internal register can be switched on either the A or B ports for output.

   Depeding on the state of the select in-puts (S0, S1, S2), and carry in/ serial in/clock enable (CI/SI/CE), the 74F807 has nine distinct operating modes:

1. Add mode w/carry in-the CI/SI/Cinput is used as a carry in signal and the STATOUT output is the carry out signal.(In add mode the COUT is NOT registered. This means the carry output signal appears at the STATOUT output one clock prior to the related data.).  In this mode, the CI/SI/CE input is added to the register contents and to the inputs. (The adder uses only the An inputs, not the Bn inputs.)

2. Add mode wo/carry in-same as above except the CI/SI/CE input is not included in the addition.

3. Count w/count enable (count) - the CI/S CE input is now used as the count enable.input and the STATOUT output is terminal count. In this mode the CI/SI/CE input must be high to enable the count function. The register contents are incremented by one.

4. Count w/count enable (hold)- same  above except no incrementing occurs.

5. Count wo/count enable - same as number 3 except the CI/SI/CE  input has no control over counting or holding.

6. Shift -The CI/SI/CE  input now becomthe serial input and the STATOUT output becomes the serial output. In this mode the CI/SI/CE input is shifted into the Q0 register, Q0 into the Q1 register etc. The Q7 register is shifted into the STATOUT.

7. Load A inputs -The CI/SI/CE  input has no bearing in either of the load modes. The STATOUT output becomes the parity out.The parity out is high for an odd number of registered bits high, and low for even number of registered bits high (even parity). In this mode the An inputs are loaded into the internal register and output to the B bus. If OEA = low the internal register would wrap around and be loaded again.

8. Load B inputs - same as number except the A and B busses are switched.

9. Hold - Again the CI/SI/CE input is not used; the STATOUT output is still the parity out. In this mode either the A bus, B bus or both can be held with the registered data. No other operation is performed.