Features: • Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 128KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• Two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
• Two Quadrature Decoders
• FlexCAN module
• Optional On-Chip Regulator
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interface (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 49 GPIO lines
• 128-pin LQFP PackageSpecifications
| Characteristic |
Symbol |
Notes |
Min |
Max |
Unit |
| Supply voltage |
VDD_IO |
|
- 0.3 |
4.0 |
V |
| ADC Supply Voltage |
VDDA_ADC,
VREFH |
VREFH must be
less than or equal
to VDDA_ADC |
- 0.3 |
4.0 |
V |
| Oscillator / PLL Supply Voltage |
VDDA_OSC_PLL |
|
- 0.3 |
4.0 |
V |
| Internal Logic Core Supply Voltage |
VDDA_CORE |
OCR_DIS is High |
- 0.3 |
4.0 |
V |
| Input Voltage (digital) |
VIN |
Pin Groups
1, 2, 5, 6, 9, 10 |
- 0.3 |
4.0 |
V |
| Input Voltage (analog) |
VINA |
Pin Groups
11, 12, 13 |
- 0.3 |
4.0 |
V |
| Output Voltage |
VOUT |
Pin Groups
1, 2, 3, 4, 5, 6, 7, 8 |
- 0.3 |
4.0 |
V |
| Output Voltage (open drain) |
VOD |
Pin Group 4 |
- 0.3 |
6.0 |
V |
| Ambient Temperature (Automotive) |
TA |
|
-40 |
125 |
|
| Ambient Temperature (Industrial) |
TA |
|
-40 |
105 |
|
| Junction Temperature (Automotive) |
TJ |
|
-40 |
150 |
|
| Junction Temperature (Industrial) |
TJ |
|
-40 |
125 |
|
| Storage Temperature (Automotive) |
TSTG |
|
-55 |
150 |
|
| Storage Temperature (Industrial) |
TSTG |
|
-55 |
150 |
|
DescriptionThe 56F8345 is a member of the 56800E core-based family of hybrid controllers. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8345 is well-suited for many applications. The 56F8345 includes many peripherals that are especially useful for motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, industrial control for power, lighting, and automation applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set of 56F8345 is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications.
The 56F8345 supports program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8345 also provides two external dedicated interrupt lines and up to 49 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F8345 hybrid controller includes 128KB of Program Flash and 8KB of Data Flash (each programmable through the JTAG port) with 4KB of Program RAM and 8KB of Data RAM.
A total of 8KB of Boot Flash of 56F8345 is incorporated for easy customer-inclusion of field-programmable
56F8345 Data Sheet
