Features: • Up to 30 MIPS operation at 60MHz core
frequency
• Up to 40 MIPS operation at 80MHz core
frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
• Hardware DO and REP loops
• 6-channel PWM Module
• Two 4-channel, 12-bit ADCs
• Serial Communications Interface (SCI)
• 8K × 16-bit words Program Flash
• 1K × 16-bit words Program RAM
• 2K × 16-bit words Data Flash
• 1K × 16-bit words Data RAM
• 2K × 16-bit words Boot Flash
• Serial Peripheral Interface (SPI)
• General Purpose Quad Timer
• JTAG/OnCETM port for debugging
• On-chip relaxation oscillator
• 11 shared GPIO
• 48-pin LQFP PackageSpecifications
| Characteristic |
Symbol |
Min |
Max |
Unit |
| Supply voltage |
VDD |
VSS 0.3 |
VSS + 4.0 |
V |
| All other input voltages, excluding Analog inputs |
VIN |
VSS 0.3 |
VSS + 5.5V |
V |
| Analog inputs ANA0-7 and VREF |
VIN |
VSS 0.3 |
VDDA+ 0.3 |
V |
| Analog inputs EXTAL, XTAL |
VIN |
VSS 0.3 |
VSSA+ 3.0 |
V |
| Current drain per pin excluding VDD, VSS, & PWM ouputs |
I |
- |
10 |
mA |
DescriptionThe 56F801 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F801 is well-suited for many applications. The 56F801 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, and industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set of 56F801 is also highly efficient for C compilers to enable rapid development of optimized control applications.
The 56F801 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F801 also provides one external dedicated interrupt lines and up to 11 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F801 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory of 56F801 can also be either bulk or page erased.
A key application-specific feature of the 56F801 is the inclusion of a Pulse Width Modulator (PWM) module. This 56F801 modules incorporates six complementary, individually programmable PWM signal outputs to enhance motor control functionality. Complementary operation permits programmable dead-time insertion,
56F801 Data Sheet
