Features: • Up to 60 MIPS at 60MHz core frequency• DSP and MCU functionality in a unified, C-efficient architecture• 32KB Program Flash• 4KB Program RAM• 8KB Data Flash• 8KB Data RAM• 8KB Boot Flash• One 6-channel PWM module• Two 3-channel 12-b...
56F8322: Features: • Up to 60 MIPS at 60MHz core frequency• DSP and MCU functionality in a unified, C-efficient architecture• 32KB Program Flash• 4KB Program RAM• 8KB Data Flash...
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Characteristic | Symbol | Notes | Min | Max | Unit |
Supply voltage | VDD_IO | - 0.3 | 4.0 | V | |
ADC Supply Voltage | VDDA_ADC, VREFH |
VREFH must be less than or equal to VDDA_ADC |
- 0.3 | 4.0 | V |
Oscillator / PLL Supply Voltage | VDDA_OSC_PLL | - 0.3 | 4.0 | V | |
Internal Logic Core Supply Voltage | VDD_CORE | OCR_DIS is High | - 0.3 | 3.0 | V |
Input Voltage (digital) | VIN | Pin Groups 1, 3, 4, 5 | - 0.3 | 6.0 | V |
Input Voltage (analog) | VINA | Pin Group 7 | - 0.3 | 4.0 | V |
Output Voltage | VOUT | Pin Groups 1, 2, 3 | - 0.3 | 4.0 | V |
Output Voltage (open drain) | VOD | GPIO pins used in open drain mode |
- 0.3 | 6.0 | V |
Ambient Temperature (Automotive) | TA | -40 | 125 | ||
Ambient Temperature (Industrial) | TA | -40 | 105 | ||
Junction Temperature (Automotive) | TJ | -40 | 150 | ||
Junction Temperature (Industrial) | TJ | -40 | 125 | ||
Storage Temperature (Automotive) | TSTG | -55 | 150 | ||
Storage Temperature (Industrial) | TSTG | -55 | 150 |
The 56F8322 and 56F8122 are members of the 56800E core-based family of hybrid controllers. Each combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of their low cost, configuration flexibility, and compact program code, the 56F8322 and 56F8122 are well-suited for many applications. These devices include many peripherals that are especially useful for automotive control (56F8322 only); industrial control and networking; motion control; home appliances; general purpose inverters; smart sensors; fire and security systems; power management; and medical monitoring applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set of 56F8322 is also highly efficient for C Compilers to enable rapid development of optimized control applications.
The 56F8322 and 56F8122 support program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. These 56F8322 also provide one external dedicated interrupt line and up to 21 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.