Features: The 56F8300 Series of devices is the latest set of components using the highly successful 56800/E hybrid 16-bit MCU/DSP core. The 56F8300 Series utilizes the enhanced 56800 core, 56800E, that has a number of improvements over the 56800 and blurs the line between 16-bit and 32-bit archite...
56F8300: Features: The 56F8300 Series of devices is the latest set of components using the highly successful 56800/E hybrid 16-bit MCU/DSP core. The 56F8300 Series utilizes the enhanced 56800 core, 56800E, t...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
The 56F8300 Series of devices is the latest set of components using the highly successful 56800/E hybrid 16-bit MCU/DSP core. The 56F8300 Series utilizes the enhanced 56800 core, 56800E, that has a number of improvements over the 56800 and blurs the line between 16-bit and 32-bit architectures.
Key features of the 56800E core include:
• Fully source code-compatible with the 56800 core
• Efficient 16-bit engine with dual Harvard architecture
• Up to 200 Million Instructions Per Second (MIPS) at 200MHz core frequency
• Single-cycle 16 * 16-bit parallel Multiplier-Accumulator (MAC)
• Four (4) 36-bit accumulators, including extension bits
• Flexible bit manipulation unit with 16- & 32-bit bidirectional shifter
• Parallel instruction set with unique addressing modes
• Hardware DO and REP loops (zero overhead)
• Three (3) internal address buses and one (1) external address bus
• Four (4) internal data buses and one (1) external data bus
• Internal 32-bit data buses
• Move operations supporting native single cycle 8-, 16-, and 32-bit data types
• Linear memory space: 4MB program and 32MB data
• Instruction set supports both MCU and DSP functions
• Five (5) software interrupt levels
• Fast interrupt support with arbitrary ISR length
• 19 different controller-style addressing modes and instructions for compact code
• Designed for efficient C-compiler and local variable support
• Software subroutine and interrupt stack, with depth limited only by memory
• JTAG/Enhanced OnCE debug interface for real-time hardware debugging
The 56F8300 Series couples this impressive core with an equally impressive set of peripherals, internal memories, and operating temperature range. Here are some of the features of the 56F8300 processor Series:
• As many as 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
• Harvard architecture permits as many as three simultaneous accesses to program and data memory
• Wide range of on-chip memory configurations
• Flash memory security
• Operating range of -40°C to +125°C (at full speed)
The 56F8300 is source code-compatible with all 56F800 components, creating a very easy migration path for users who require increased performance or memory space. The 56F8300 shares many of the peripherals, instruction set, and toolset of Motorola's 8/16 MCU families, providing an excellent roadmap for users of these components.