Features: • Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• 64K × 16-bit words Program Flash
• 1K × 16-bit words Program RAM
• 4K × 16-bit words Data Flash
• 4K × 16-bit words Data RAM
• Up to 64K × 16-bit words external memory
expansion each for Program and Data memory
• JTAG/OnCE™ for debugging
• General Purpose Quad Timer
• MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
• 8-channel Programmable Chip Select
• 10-channel, 12-bit ADC
• Synchronous Serial Interface (SSI)
• Serial Port Interface (SPI)
• Serial Communications Interface (SCI)
• Time-of-Day (TOD) Timer
• 128-pin LQFP Package
• 16-dedicated and 48 shared GPIOPinout
Specifications
| Characteristic |
Symbol |
Min |
Max |
Unit |
| Supply voltage, core |
VDD1 |
VSS - 0.3 |
VSS + 3.0 |
V |
Supply voltage, IO
Supply voltage, Analog
Supply voltage, ADC |
VDDIO2
VDDA2
VDDA_ADC |
VSSIO - 0.3
VSSA - 0.3
VSSA_ADC-0.3 |
VSSIO + 4.0
VSSA + 4.0
VSSA_ADC+0.3 |
V |
Digital input voltages
Analog input voltages (XTAL, EXTAL)
Analog input voltages (ANA0-7, VREF) |
VIN
VINA
VIN_ADC |
VSSIO - 0.3
VSSA - 0.3
VSSA_ADC-0.3 |
VSSIO + 5.5
VDDA + 0.3
VSSA_ADC+0.3 |
V |
Current drain per pin excluding VDD, VSS, VDDA,
VSSA,VDDIO, VSSIO |
I |
- |
10 |
mA |
| Junction temperature |
TJ |
- |
150 |
|
| Storage temperature range |
TSTG |
-55 |
150 |
|
DescriptionThe 56F827 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution for general purpose applications. Because of its low cost, configuration flexibility, and compact program code, the 56F827 is well-suited for many applications. The 56F827 includes many peripherals that are especially useful for applications such as: noise suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic alarms, and telephony.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set of 56F827 is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications.
The 56F827 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F827 also provides two external dedicated interrupt lines, and up to 64 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F827 controller includes 64K words (16-bit) of Program Flash and 4K words of Data Flash (each programmable through the JTAG port) with 1K words of Program RAM and 4K words of Data RAM. It also supports program execution from external memory. The 56800 core is capable of accessing two data operands from the on-chip Data RAM per instruction cycle.
This controller 56F827 also provides a full set of standard programmable peripherals that include one 10-input, 12- bit Analog-to-Digital Converters (ADC), one Synchronous Serial Interface (SSI), two Serial Peripheral Interfaces (SPI), three Serial Communications Interfaces (SCI). (Note: The second SPI is multiplexed with the second and third SCIs, giving the option to select a second SPI or two additional SCIs.) This hybrid controller 56F827 also provides one Programmable Chip Select (PCS), and one Quad Timer. The SCI, SSI, SPI, Quad Timer A, and select address and data lines can be used as General Purpose Input/Outputs (GPIOs) if those functions are not required.
56F827 Data Sheet
