Features: • Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)• Four 36-bit accumu...
56F8037: Features: • Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequ...
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Characteristic |
Symbol |
Notes |
Min |
Max |
Unit |
Supply Voltage Range |
VDD |
Pin Groups 1, 2 |
-0.3 |
4.0 |
V |
The 56F8037 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8037 is well-suited for many applications. The 56F8037 includes many peripherals that are especially useful for industrial control, motion control, home appliances, general purpose inverters, smart sensors, fire and security systems, switched-mode power supply, power management, and medical monitoring applications.
The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set of 56F8037 is also highly efficient for C compilers to enable rapid development of optimized control applications.
The 56F8037 supports program execution from internal memories. Two data operands can be accessed