Features: • Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
• 31.5K * 16-bit words Program Flash
• 512 * 16-bit words Program RAM
• 4K * 16-bit words Data Flash
• 2K * 16-bit words Data RAM
• 2K * 16-bit words Boot Flash
• Up to 64K * 16-bit words each of external
Program and Data memory
• 6-channel PWM module
• Two 4-channel 12-bit ADCs
• Quadrature Decoder
• CAN 2.0 B module
• Serial Communication Interface (SCI)
• Serial Peripheral Interface (SPI)
• Up to two General Purpose Quad Timers
• JTAG/OnCETM port for debugging
• 16 shared GPIO lines
• 100pin LQFP packagePinout
Specifications
| Characteristic |
Symbol |
Min |
Max |
Unit |
| Supply voltage |
VDD |
VSS 0.3 |
VSS + 4.0 |
V |
| All other input voltages, excluding Analog inputs |
VIN |
VSS 0.3 |
VSS + 5.5V |
V |
| Analog inputs ANA0-7 and VREF |
VIN |
VSS 0.3 |
VDDA+ 0.3 |
V |
| Analog inputs EXTAL and XTAL |
VIN |
VSS 0.3 |
VSSA+ 3.0 |
V |
| Current drain per pin excluding VDD,VSS,PWM ouputs,TCS,VPP, VDDA, VSSA |
I |
- |
10 |
mA |
DescriptionThe 56F803 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F803 is well-suited for many applications. The 56F803 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, and industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set of 56F803 is also highly efficient for C compilers to enable rapid development of optimized control applications.
The 56F803 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F803 also provides two external dedicated interrupt lines, and up to 16 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F803 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It also supports program execution from external memory.
A total of 2K words of Boot Flash of 56F803 is incorporated for easy customer-inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas.
56F803 Data Sheet
