4MBIT

` Single 3.0 V read, program, and erase
   Minimizes system level power requirements
` Compatible with JEDEC-standard commands
   Uses same software commands as 2E PROMs
` Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(I) (Package suffix: PFTN Normal Bend Type, PFTR Reversed Bend Type)
   44-pin SOP (Package suffix: PF)
   48-pin CSOP (Package suffix: PCV)
   48-ball FBGA (Package suffix: PBT)
` Minimum 100,000 program/erase cycles
` High performance
   70 ns maximum access time
` Sector erase architecture
   One 8K word, two 4K words, one 16K word, and seven 32K words sectors in word mode
   One 16K byte, two 8K bytes, one 32K byte, and seven 64K bytes sectors in byte modeAny combination of sectors can be concurrently erased. Also supports full chip erase
` Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
` Embedded Erase  Algorithms^TM
   Automatically preprograms and erases the chip or any sector
` Embedded Program  Algorithms<sup>TM</sup>
   Automatically writes and verifies data at specified address
`  Data Polling and Toggle Bit feature for detection of program or erase cycle completion
` Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
` Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode
`  Low VCC write inhibit   2.5 V
` Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device

Storage Temperature......................................................................................................55to +125
Ambient Temperature with Power Applied .......................................................................40 to +85
Voltage with respect to Ground All pins except A9, OE, R_ESET (Note 1)...................0.5 V to V_CC+0.5 V
V_CC (Note 1) ..................................................................................................................0.5 V to +5.5 V
A9, OE, and RESET (Note 2)..........................................................................................0.5 V to +13.0 V

Notes:
1. Minimum DC voltage on input or I/O pins are 0.5 V. During voltage transitions, inputs may negative overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are V_CC +0.5 V. During voltage transitions, outputs may positive overshoot to V_CC +2.0 V for periods of up to 20 ns.

2. Minimum DC input voltage on A9, OE and RESET pins are 0.5 V. During voltage transitions, A9, OE and R_ESET pins may negative overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9, OE and R_ESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of up to 20 ns. Voltage difference between input voltage and supply voltage (V_IN V_CC) do not exceed 9 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

The MBM29LV400TC/BC are a 8M-bit, 3.0 V-only Flash memory organized as 512K bytes of 8 bits each or 256K ords of 16 bits each. The MBM29LV400TC/BC are offered in a 48-pin TSOP(I), 44-pin SOP, 48-pin CSOP,  and 8-ball FBGA packages. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The MBM29LV400TC/BC can also be reprogrammed in standard EPROM programmers.

The standard MBM29LV400TC/BC offer access times 70 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the MBM29LV400TC/BC have separate chip enable (CE), write enable (WE), and output enable (OE) controls.

The MBM29LV400TC/BC are pin and command set compatible with JEDEC standard E PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the MBM29LV400TC/BC is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV400TC/BC are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector of the MBM29LV400TC/BC can be programmed and verified in about 0.5 seconds.

Erase of the MBM29LV400TC/BC is accomplished by executing the erase command sequence. This will invoke the Embedded Erase lgorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the MBM29LV400TC/BC automatically time the erase pulse widths and verify proper cell margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The MBM29LV400TC/BC also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29LV400TC/BC are erased when shipped from the factory.

The MBM29LV400TC/BC feature single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector of the MBM29LV400TC/BC automatically  inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode.

Fujitsu's Flash technology of MBM29LV400TC/BC combines years of EPROM and 2E PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29LV400TC/BC memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.