41002

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.

separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications of the ALVCH16260 include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This ALVCH16260 also is useful in memory interleaving applications. Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available address and/or data transfer.

The output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions.

The OE1B and OE2B control signals of ALVCH16260 also allow bank control in the A-to-B direction. Address and/or data information can be stored using the internal storage latches. The latch-enable LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input of ALVCH16260 is high, the latch is transparent. When the latchenable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high.

The ALVCH16260 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

The ALVCH16260 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs eliminates the need for pull-up/down resistors.