Features: True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access Commercial: 15/20/25/35/55ns (max.) Industrial: 20/25/35/55ns (max.) Low-power operation IDT70V05SActive: 400mW (typ.)Standby: 3.3mW (typ.) IDT70V05LActive: 380mW (typ.)Standby: 66...
40874: Features: True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access Commercial: 15/20/25/35/55ns (max.) Industrial: 20/25/35/55ns (max.) Low-power o...
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Symbol |
Rating |
Commercial
& Industrial |
Unit |
VTERM |
Terminal Voltage with respect to GND |
-0.5 to +7.0 |
V |
VTER(2) |
Terminal Voltage |
-55 to +125 |
°C |
TSTG |
Temperature Under Bias |
-65 to +150
|
°C |
IOUT |
DC Output Current |
50
|
mA |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V.
The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bitor- more word systems. Using the IDT MASTER/SLAVE Dual-Port SRAM approach in 16-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional discrete logic.
This IDT70V05 provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 400mW of power. The IDT70V05 is packaged in a ceramic 68-pin PGA and PLCC and a 64-pin thin quad flatpack (TQFP).