40874

Features: True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access Commercial: 15/20/25/35/55ns (max.) Industrial: 20/25/35/55ns (max.) Low-power operation IDT70V05SActive: 400mW (typ.)Standby: 3.3mW (typ.) IDT70V05LActive: 380mW (typ.)Standby: 66...

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SeekIC No. : 004230314 Detail

40874: Features: True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access Commercial: 15/20/25/35/55ns (max.) Industrial: 20/25/35/55ns (max.) Low-power o...

floor Price/Ceiling Price

Part Number:
40874
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/20

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Product Details

Description



Features:

True Dual-Ported memory cells which allow simultaneous reads of the same memory location
High-speed access
Commercial: 15/20/25/35/55ns (max.)
Industrial: 20/25/35/55ns (max.)
Low-power operation
IDT70V05S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
IDT70V05L
Active: 380mW (typ.)
Standby: 660 µW (typ.)
IDT70V05 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than one device
M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
 Full on-chip hardware support of semaphore signaling between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available for selected speeds



Pinout

  Connection Diagram
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking



Specifications

Symbol
Rating
Commercial
& Industrial
Unit
VTERM
Terminal Voltage
with respect to GND
-0.5 to +7.0
V
VTER(2)
Terminal Voltage
-55 to +125
°C
TSTG
Temperature
Under Bias
-65 to +150
°C
IOUT
DC Output Current
50
mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V.




Description

The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bitor- more word systems. Using the IDT MASTER/SLAVE Dual-Port SRAM approach in 16-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional discrete logic.

This IDT70V05 provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 400mW of power. The IDT70V05 is packaged in a ceramic 68-pin PGA and PLCC and a 64-pin thin quad flatpack (TQFP).




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