37996

Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these
extremes.
Note: 1. V_DD3 refers to all of the nominal 3.3V power supplies (V_DDH, V_OSC, V_DDSD). VDD refers to all of the nominal .8V power supplies (V_DD, V_MTR).
          2. During Normal Mode operation VDD3 is always available as specified
          3. During Fail-safe Mode operation VDD3 may be not available.

The 37996 is an integrated circuit implementing an advanced mixed analogue and digital solution to perform the signal processing of a AM/FM channel. The HW&SW architecture has been devised so to have a digital equalization of the FM/AM channel; hence a real rejection of adjacent channels and any other signals interfering with the listening of the desired station. In severe Multiple Paths conditions, the reception is improved to get the audio with high quality.

The algorithm is self-adaptive, thus it requires no "on-the-field" adjustments after the parameters optimization.The chip embeds a Band Pass Sigma Delta Analogue to Digital Converter for 10.7MHz IF conversion from a "tuner device" (it is highly recommended the 37996).

The internal 24bit-DSP allows some flexibility in the algorithm implementation, thus giving some freedom for customer required features. The total processing power offers a significant headroom for customer's software requirement, even when the channel equalization and the decoding software is running. The Program and Data Memory space can be loaded from an external non volatile memory via I²C or SPI.

The oscillator module works with an external 74.1MHz quartz crystal. It has very low Electro Magnetic Interference,
as it introduces very low distortion, and in any case any harmonics fall outside the Radio bandwidth. The companion tuner device receives the reference clock through a differential ended interface, which works off the Oscillator module by properly dividing down the master clock frequency. That allows the overall system saving an additional crystal for the tuner.

After the IF conversion, the digitized baseband signal passes through the Base Band processing section, either FM or AM, depending on the listener selection. The FM Base Band processing comprises of Stereo Decoder,Spike Detection and Noise Blanking. The AM Noise Blanking is fully software implemented.

The internal RDS filter, demodulator and decoder features complete functions to have the output data available through either I2C or SPI interface. No DSP support is needed but at start-up, so that RDS can work in background
and in parallel with other DSP processing. This mode (RDS-only) allows current consumption saving for low power application modes.

An I2C/SPI interface is available for any control and communication with the main micro, as well as RDS data interface. The DSP SPI block embeds a 10 words FIFO for both transmit and receive channels, to lighten the DSP task and frequently respond to the interrupt from the control interface.

Serial Audio Interface (SAI) is the ideal solution for the audio data transfer, both transmit and receive: either master or slave. The flexibility of this module gives a wide choice of different protocols, including I2S. Two fully ndependent bidirectional data channels, with separate clocks allows the use of TDA7580 as general purpose digital audio processor.

A fully Asynchronous Sample Rate Converter (ASRC) is available as a peripheral prior to sending audio data out via the SAI, so that internal audio sampling rate (~36kHz and FM/AM mode) can be adapted by upconversion to any external rate.

An Inter Processor Transport Interface (HS3I, High Speed Synchronous Serial Interface) is also available for a modular system which implements Dual Tuner Diversity, thus enhancing the overall system performance. It is about a Synchronous Serial Interface which exchanges data up to the MPX rate. It has been designed to reduce the Electro Magnetic Interference toward the sensitive analogue signal from the Tuner.

General Purpose I/O registers are connected to and controlled by the DSP, by means of memory map.

A Debug and Test Interface is available for on-chip software debug as well as for internal registers read/write operation.