Features: Dual 4.0m? Max High-Side Switch with Parallel Input or SPI Control 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 AOutput Current Monitoring with Two SPI-Selectable Current RatiosSPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time, Output-OFF Open Load Detec...
33984: Features: Dual 4.0m? Max High-Side Switch with Parallel Input or SPI Control 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 AOutput Current Monitoring with Two SPI-Selectable Current...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Dual 4.0m? Max High-Side Switch with Parallel Input or SPI Control
6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 A
Output Current Monitoring with Two SPI-Selectable Current Ratios
SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time, Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog Timeout, Slew Rates, and Fault Status Reporting
SPI Status Reporting of Overcurrent, Open and Shorted Loads, Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe Pin Status, and Program Status
Enhanced -16 V Reverse Polarity V Protection PWR
Rating |
Symbol |
Value |
Unit |
ELECTRICAL RATINGS | |||
Operating Voltage Range |
VPWR |
-16 to 41 |
V |
V Supply Voltage |
VDD |
0 to 5.5 |
V |
Input/Output Voltage (Note 1) |
VIN[0:1] ,RST,FSI |
-0.3 to 7.0 |
V |
SO Output Voltage (Note 1) |
VSO |
-0.3 to V +0.3 |
V |
WAKE Input Clamp Current |
ICL(WAKE) |
2.5 |
mA |
CSNS Input Clamp Current |
ICL(CSNS) |
10 |
mA |
Output Current (Note 2) |
IHS[0:1] |
30 |
A |
Output Clamp Energy (Note 3) |
ECL[0:1] |
0.75 |
J |
ESD Voltage |
VESD1 |
±2000 |
V |
The SPI interface has a full duplex, three-wire synchronous ata transfer with four I/O lines associated with it: Serial Clock SCLK), Serial Input (SI), Serial Output (SO), and Chip Select CS).
The SI/SO terminals of the 33984 follow a first-in first-out (D7/D0) protocol with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 V CMOS logic levels.
The SPI lines perform the following functions: