2N7002KG

      The 2N7002KG (190 mA, 60 V, RDS(ON) = 2 N-Ch Small Signal MOSFET with gate protection ) is under 2 kV ESD protected, with the lower On-resistance(2 ), low input capacitance(25 pF), low input and output leakage, fast switching performance(25 nS), low threshold(2V(Typ.)). And its weight is 0.07800g (Approximately), made in the code of K7K.
      The 2N7002KG can be used in the areas of solid-state relays, drivers(Relays, Solenoids, Lamps Hammers, Display, Memories, Transistors, etc.), direct logic-level interface(TTL/CMOS), battery operated systems.Some parameters are got. V_DS(Drain-Source Voltage)=60V, V_GS(Gate-Source Voltage)=±20V, I_D(Continuous Drain Current, Surface mounted on FR4 board.)=300mA(@T_A=25°C)/190mA(@TA=100°C), I_DM(Pulsed Drain Current, Pulse width limited by maximum junction temperature)=800, P_D(Power Dissipation, Surface mounted on FR4 board)=0.35W(@TA=25°C)/0.14W(@TA=100°C), R_JA(Thermal Resistance Junction-Ambient)=350°C/W, T_J, T_STG(Operating Junction and Storage Temperature)=-55 to +150 °C.And the electrical properties are V_(BR)DSS(Drain-Source Breakdown Voltage, @ V_GS = 0, I_D = 10uA)=60V(min), V _GS(th) (Gate-Threshold Voltage, @ V_DS = V_GS, I_D = 250uA)=1.0(min)/2.5(max)V, g_fs(Forward Transconductance, @ V_DS = 10V, I_D = 200 mA, for DESIGN AID ONLY, not subject to production testing)=100mS, I_GSS(max)(Gate-Body Leakage Current)=±10 A(V_DS = 0, V_GS = ±20V)/±150nA(V_DS = 0, V_GS = ±10V)/±1000nA(V_DS=0,V_GS=±10V,TJ=85°C)/±100 nA(V_DS = 0, V_GS = ±5V), I _DSS(max) (Zero Gate Voltage Drain Current)=10nA(V_DS = 50, V_GS = 0)/100nA(V_DS = 50V, V_GS=0, T_J=85°C)/1A (V_DS = 60V, V_GS = 0)/500A(V_DS=60V, V_GS=0, T_J=125°C), I_D(min)(ON)(On-State Drain Current, For DESIGN AID ONLY, not subject to production testing)=800mA(VGS = 10V, V_DS = 7.5V)/500mA(V_GS = 4.5V, V_DS = 10V), rDS(ON)(MIN)(Drain-Source On-Resistance, For DESIGN AID ONLY, not subject to production testing)=2(V_GS = 10V, I_DS = 500mA)/4(V_GS = 4.5V, I_DS = 200mA), V _DS(ON) (Diode Forward Voltage )1.3V(max)(I_S = 200mA, V_GS =0). For the dynamic(For DESIGN AID ONLY, not subject to production testing), Q_g(Total Gate Charge)=0.4(typ)nC/0.6(max)nC(@ V_DS=10V,V_GS=4.5V,I_D=250mA), (typ.)C_iss(input Capacitance)/C_oss(Output Capacitance)/C_rss(Reverse Transfer Capacitance)=30pF/6pF/2.5pF(all @ V_DS=25V, V_GS=0V, f=1MHz). For Switching(For DESIGN AID ONLY, not subject to production testing; pulse test: P_W 300s duty cycle 2% ), (min.)t_(ON) (Turn-On Time)/t_(OFF) (Turn-Off Time)=25nS/35n (V_DD=30V,R_L=150,I_D= 200mA,V_GEN=10V,R_G=10).