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28F640L18

Features: ` High performance Read-While-Write/Erase-85 ns initial access-54 MHz with zero wait state, 14 ns clock-todata output synchronous-burst mode-25 ns asynchronous-page mode-4-, 8-, 16-, and continuous-word burst mode-Burst suspend-Programmable WAIT configuration-Buffered Enhanced Factory P...

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28F640L18: Features: ` High performance Read-While-Write/Erase-85 ns initial access-54 MHz with zero wait state, 14 ns clock-todata output synchronous-burst mode-25 ns asynchronous-page mode-4-, 8-, 16-, and ...

28F640L18 Data Sheet

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Part Number:
28F640L18
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

` High performance Read-While-Write/Erase
-85 ns initial access
-54 MHz with zero wait state, 14 ns clock-todata
  output synchronous-burst mode
-25 ns asynchronous-page mode
-4-, 8-, 16-, and continuous-word burst mode
-Burst suspend
-Programmable WAIT configuration
-Buffered Enhanced Factory Programming
  (BEFP) at 5 s/byte (Typ)
-1.8 V low-power buffered programming at
7 s/byte (Typ)
` Architecture
-Asymmetrically-blocked architecture
-Multiple 8-Mbit partitions: 64-Mbit and 128-
  Mbit devices
-Multiple 16-Mbit partitions: 256-Mbit devices
-Four 16-Kword parameter blocks: top or
  bottom configurations
-64-Kword main blocks
-Dual-operation: Read-While-Write (RWW) or
  Read-While-Erase (RWE)
-Status Register for partition and device status
` Power
-VCC (core) = 1.7 V - 2.0 V
-VCCQ (I/O) = 1.35 V - 2.0 V, 1.7 V - 2.0 V
-Standby current: 30 A (Typ) for 256-Mbit
-4-Word synchronous read current: 15 mA (Typ) at 54 MHz
-Automatic Power Savings mode
` Security
-OTP space:
• 64 unique factory device identifier bits
• 64 user-programmable OTP bits
• Additional 2048 user-programmable OTP bits
-Absolute write protection: VPP = GND
-Power-transition erase/program lockout
-Individual zero-latency block locking
-Individual block lock-down
` Software
-20 s (Typ) program suspend
-20 s (Typ) erase suspend
-Intel® Flash Data Integrator optimized
-Basic Command Set (BCS) and Extended
  Command Set (ECS) compatible
-Common Flash Interface (CFI) capable
` Quality and Reliability
-Expanded temperature: 25° C to +85° C
-Minimum 100,000 erase cycles per block
-ETOX™ VIII process technology (0.13 m)
` Density and Packaging
-64-, 128-, and 256-Mbit density in VF BGA packages
-128/0 and 256/0 density in SCSP
-16-bit wide data bus


Specifications

Parameter Maximum Rating Notes
Temperature under bias 25 °C to +85 °C  
Storage temperature 65 °C to +125 °C  
Voltage on any signal (except VCC, VPP) 0.5 V to +2.5 V 1
VPP voltage 0.2 V to +10 V 1,2,3
VCC voltage 0.2 V to +2.5 V 1
VCCQ voltage 0.2 V to +2.5 V 1
Output short circuit current 100 mA 4
Notes:
1. Voltages shown are specified with respect to VSS. Minimum DC voltage is 0.5 V on input/output
signals and 0.2 V on VCC, VCCQ, and VPP. During transitions, this level may undershoot to 2.0 V for
periods < 20 ns. Maximum DC voltage on VCC is VCC +0.5 V, which, during transitions, may overshoot
to VCC +2.0 V for periods < 20 ns. Maximum DC voltage on input/output signals and VCCQ is VCCQ
+0.5 V, which, during transitions, may overshoot to VCCQ +2.0 V for periods < 20 ns.
2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns.
3. Program/erase voltage is typically 1.7 V 2.0 V. 9.0 V can be applied for 80 hours maximum total, to
any blocks for 1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling
capability.
4. Output shorted for no more than one second. No more than one output shorted at a time.


Description

The Intel StrataFlash® wireless memory (L18) device 28F640L18 is the latest generation of Intel StrataFlash® memory devices featuring flexible, multiple-partition, dual operation. It provides high performance synchronous-burst read mode and asynchronous read mode using 1.8 V lowvoltage, multi-level cell (MLC) technology.

28F640L18 enables background programming or erasing to occur in one partition while code execution or data reads take place in another partition. This dual-operation architecture also allows a system to interleave code operations while program and erase operations take place in the background. The 8-Mbit or 16-Mbit partitions allow system designers to choose the size of the code and data segments. The L18 wireless memory device is manufactured using Intel 0.13 m ETOX™ VIII process technology. 28F640L18 is available in industrystandard chip scale packaging.




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