25LC256

Features:

• Max. clock 10 MHz
• Low-power CMOS technology
- Max. Write Current: 5 mA at 5.5V, 10 MHz
- Read Current: 5 mA at 5.5V, 10 MHz
- Standby Current: 1 A at 5.5V
• 32,768 x 8-bit organization
• 64 byte page
• Self-timed ERASE and WRITE cycles (5 ms max.)
• Block write protection
- Protect none, 1/4, 1/2 or all of array
• Built-in write protection
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential read
• High reliability
- Endurance: 1,000,000 erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• Temperature ranges supported;
- Industrial (I): -40 to +85
- Automotive (E): -40 to +125
• Standard and Pb-free packages available




Pinout






Specifications

Parameter Name	Value
Density	256 Kbit (x8)
Max. Clock Freq.	10 MHz
Page Size (bytes)	64
Write Protect	Quarter, Half, Whole Array
Endurance	1,000,000
Op. Volt Range (V)	2.5 to 5.5
Temp Range (°C)	-40°C to +125°C

VCC............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ..................................................................................................... -0.6V to VCC + 1.0V
Storage temperature ................................................................................................................................-65 to 150
Ambient temperature under bias............................................................................................................... -40to 125
ESD protection on all pins.........................................................................................................................................4 kV




Description

The Microchip Technology Inc. 25AA256/25LC256 (25XX256*) are 256k-bit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface™ (SPI™) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select ( CS ) input.

Communication to the device can be paused via the hold pin (HOLD). While 25LC256 is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts.

The 25XX256 is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging including 8-lead DFN and 8-lead TSSOP. Pb-free (Pure Sn) finish is also available.