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The PA7572 is a member of the Programmable Electrically rasable Logic (PEEL™) Array family based on Anachip's MOS EEPROM technology. PEEL™ Arrays free esigners from the limitations of ordinary PLDs by roviding the architectural flexibility and speed needed for oday's programmable logic designs. The PA7572 offers a ersatile logic array architecture with 24 I/O pins, 14 input ins and 60 registers/latches (24 buried logic cells, 12 input egisters/latches, 24 buried I/O registers/latches). PA7572's logic rray implements 100 sum-of-products logic functions ivided into two groups each serving 12 logic cells. Each roup shares half (60) of the 120 product-terms available.

The PA7572's logic and I/O cells (LCCs, IOCs) are xtremely flexible with up to three output functions per cell a total of 72 for all 24 logic cells). Cells are configurable as , T, and JK registers with independent or global clocks, esets, presets, clock polarity, and other features, making the PA7572 suitable for a variety of combinatorial, ynchronous and asynchronous logic applications. The A7572 supports speeds as fast as 13ns/20ns (tpdi/tpdx) nd 66.6MHz (fMAX) at moderate power consumption 40mA (100mA typical). Packaging includes 40-pin DIP nd 44-pin PLCC (see Figure 1). Anachip and popular hird-party development tool manufacturers provide evelopment and programming support for the PA7572.