Features: ·High Frequency = 100, 125, 133MHz
·Package:
- 208 Plastic Ball Grid Array (PBGA), 16 x 22mm
·3.3V ±0.3V power supply for core and I/Os
·Fully Synchronous; all signals registered on pos i tive edge of system clock cycle
Internal pipelined operation; column address can be changed every clock cycle
·Internal banks for hiding row access/precharge
·Programmable Burst length 1,2,4,8 or full page
·8192 refresh cycles
·Commercial, Industrial and Military Temperature Rang es
·Organized as 32M x 72
·Weight: W332M72V-XSBX - 2.0 grams typical
Specifications
|
Parameter
|
|
Unit |
| Voltage on VCC, VCCQ Supply relative to Vss |
-1 to 4.6 |
V |
| Voltage on NC or I/O pins relative to Vss |
-1 to 4.6 |
V |
| Operating Temperature TA (Mil) |
-55 to +125 |
°C |
| Operating Temperature TA (Ind) |
-40 to +85 |
°C |
| Storage Temperature, Plastic |
-55 to +125 |
°C |
DescriptionThe 256MByte (2Gb) SDRAM is a high-speed CMOS, dy nam ic ran dom-access, memory using 5 chips containing 536,870,912 bits. Each chip is internally confi gured as a quad-bank DRAM with a syn chro nous interface. Each of the chip's 134,217,728-bit banks is or ga nized as 8,192 rows by 1,024 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; ac cess es start at a selected location and continue for a pro grammed number of locations in a programmed se quence. Ac cess es be gin with the registration of an ACTIVE com mand, which is then fol lowed by a READ or WRITE com mand. The address bits reg is tered coincident with the AC TIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0- 12 select the row). The address bits reg is tered co in ci dent with the READ or WRITE com mand are used to se lect the starting col umn lo ca tion for the burst ac cess.
The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be en abled to provide a self-timed row precharge that is initiated at the end of the burst sequence.
The 2Gb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is com pat i ble with the 2n rule of prefetch architectures, but it also allows the column ad dress to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while ac cess ing one of the other three banks will hide the precharge cycles and provide seam less, highspeed, random-access op er a tion.
The 2Gb SDRAM is designed to operate at 3.3V. An auto refresh mode is provided, along with a power-saving, power-down mode.
200809272149249181 Data Sheet
