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The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1M x 18 ynchronous flow through Burst SRAM designed specifically o support unlimited true back-to-back Read/Write operations ith no wait state insertion. The CY7C1371D/CY7C1373D is quipped with the advanced No Bus Latency (NoBL) logic equired to enable consecutive Read/Write operations with ata being transferred on every clock cycle. This feature ramatically improves the throughput of data through the RAM, especially in systems that require frequent Write-Read ransitions.

All synchronous inputs pass through input registers controlled y the rising edge of the clock. The clock input is qualified by he Clock Enable (CEN) signal, which when deasserted uspends operation and extends the previous clock cycle. aximum access delay from the clock rise is 6.5 ns (133-MHz evice).

Write operations are controlled by the two or four Byte Write elect (BWX) and a Write Enable (WE) input. All writes are onducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an synchronous Output Enable (OE) provide for easy bank election and output tri-state control. To avoid bus contention, he output drivers are synchronously tri-stated during the data ortion of a write sequence.