200809272134399568

`Access Times of 35ns (SRAM) and 150ns (EEPROM)
` Access Times of 45ns (SRAM) and 120ns (EEPROM)
` Access Times of 70ns (SRAM) and 300ns (EEPROM)
` Packaging
• 66 pin, PGA Type, 1.075" square HIP, Hermetic eramic HIP (H1) (Package 400)
• 68 lead, Hermetic CQFP (G2T), 22mm (0.880") quare (Package 509). Designed to fi t JEDEC 68 ead 0.990" CQFJ footprint (FIGURE 2)
` 128Kx16 SRAM
` 128Kx16 EEPROM
` Organized as 128Kx16 of SRAM and 128Kx16 of EPROM Memory with separate Data Buses
` Both blocks of memory are User Confi gurable as 56Kx8
` Low Power CMOS LOCK DIAGRAM IN DESCRIPTION D0-15 EEPROM Data Inputs/Outputs D0-15 SRAM Data Inputs/Outputs 0-16 Address Inputs WE#1-2 SRAM Write Enable CS#1-2 SRAM Chip Selects E# Output Enable CC Power Supply ND Ground C Not Connected WE#1-2 EEPROM Write Enable CS#1-2 EEPROM Chip Select op View IGURE 1 WSE128K16-XH1X PIN ONFIGURATION
` Commercial, Industrial and Military Temperature anges
` TTL Compatible Inputs and Outputs
` Built-in Decoupling Caps and Multiple Ground Pins or Low Noise Operation
` Weight - 13 grams typical