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200809272131423185

Features: · Integrated T3/E3 Line Interface Unit· Integrated Jitter Attenuator that can be selected either in Receive or Transmit path· Flexible integrated Clock Multiplier that takes single frequency clock and generates either DS3 or E3 frequency.· 8/16 bit UTOPIA Level I and II and PPP Multi-PHY...

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200809272131423185: Features: · Integrated T3/E3 Line Interface Unit· Integrated Jitter Attenuator that can be selected either in Receive or Transmit path· Flexible integrated Clock Multiplier that takes single frequen...

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Part Number:
200809272131423185
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/17

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Product Details

Description



Features:

· Integrated T3/E3 Line Interface Unit
· Integrated Jitter Attenuator that can be selected either in Receive or Transmit path
· Flexible integrated Clock Multiplier that takes single frequency clock and generates either DS3 or E3 frequency.
· 8/16 bit UTOPIA Level I and II and PPP Multi-PHY Interface operating at 25, 33 or 50 MHz.
· HDLC Controller that provides the mapping/ extraction of either bit or byte mapped encapsulated packet from DS3/E3 Frame.
· Contains on-chip 16 cell FIFO (configurable in depths of 4, 8, 12 or 16 cells), in both the Transmit (TxFIFO) and Receive Directions (RxFIFO)
· Contains on-chip 54 byte Transmit and Receive OAM Cell Buffer for transmission, reception and processing of OAM Cells
· Supports ATM cell or PPP Packet Mapping
· Supports M13 and C-Bit Parity Framing Formats
· Supports DS3/E3 Clear-Channel Framing.
· Includes PRBS Generator and Receiver
· Supports Line, Cell, and PLCP Loop-backs
· Interfaces to 8 Bit wide Intel, Motorola or PowerPC
· Low power 3.3V, 5V Input Tolerant, CMOS
· Available in 456 Lead PBGA Package
· JTAG Interface


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