Details on Intel’s Ivy Bridge

Published:2012/2/20 20:53:00 Author:Phyllis From:SeekIC

Intel’s Ivy Bridge was the first processors to use the company’s 22 nm tri-gate technology. At least four major variants of the chip are planned. Ivy Bridge packs 20 channels of PCI Express Gen 3 interconnect and a Displayport controller, Intel’s first chip to integrate PCIe. The move marks one small step into the long term quest of what an Intel executive called terascale-class clients.

The first Ivy Bridge chip was designed for a range of desktop, notebook, embedded and single-socket server systems with up to 8 Mbytes cache. Like previous Intel parts, it integrates a memory controller and graphics, now upgraded to support DDR3L DRAMs and Microsoft DirectX 11.0 graphics APIs.

Intel has spent a lot of time on the modularity of this die to create different flavors of it very quickly. Specifically the largest die includes four x86 cores and a large graphics block. It can be chopped along its x- and/or y-axis using automated generation tools to create versions with two cores or a smaller graphics block.

Ivy Bridge is Intel’s first client chip to support low power 1.35V DDR3L and DDR power gating in standby mode. It handles up to 1,600 MTransfers/s as well as 1.5V DDR3. A new write assist cache circuit provides an average 100 millivolt power reduction. The Displayport block supports three simultaneous displays including one 1.6 GHz and two 2.7 GHz links with four lanes each.

The PCIe receiver uses a continuous time linear equalizer with 32 gain control levels and a transmitter with a three-tap digital FIR filter. The PCIe block also supports on die testing for jitter as well as timing and voltage margin measurements.

The chip’s x86 and graphics cores can scale in data rates at 100 and 50MHz increments respectively. Overall, the chip supports five power planes and 180 clock islands that can be separately gated.

Terahertz systems consume as much as three kilowatts today but could be reduced to 20W by the end of the decade using a broad variety of techniques, he said. The techniques include optimizing chips to work at near threshold voltage levels, a subject of several Intel papers at ISSCC. Lower power internal and external interconnects are also needed.

3-D IC packaging will be needed to lower power memory. Toward that end Intel is working with Micron and others on its Hypercube stacked memory design. The design could boost memory bandwidth ten-fold while cutting power to eight pico-joules per bit, down from 50-75 pj/bit in today’s DDR3.

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