XC3S1000, XC3S1000 FG256, XC3S1000 FG456 Selling Leads, Datasheet
MFG:XILINX Package Cooled:ORG PACKING D/C:08+
XC3S1000, XC3S1000 FG256, XC3S1000 FG456 Datasheet download
Part Number: XC3S1000
MFG: XILINX
Package Cooled: ORG PACKING
D/C: 08+
XC3S1000, XC3S1000 FG256, XC3S1000 FG456
- Table of contents:
Info of XC3S1000
Info of XC3S1000 FG256
Info of XC3S1000 FG456
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About XC3000
PDF/DataSheet Download
Datasheet: XC3000
File Size: 748869 KB
Manufacturer: XILINX [Xilinx, Inc]
Download : Click here to Download
About XC3000
PDF/DataSheet Download
Datasheet: XC3000
File Size: 748869 KB
Manufacturer: XILINX [Xilinx, Inc]
Download : Click here to Download
About XC3000
PDF/DataSheet Download
Datasheet: XC3000
File Size: 748869 KB
Manufacturer: XILINX [Xilinx, Inc]
Download : Click here to Download
XC3S1000 Maximum Ratings
| Symbol | Description | Conditions | Min | Max | Units | |
| VESD | Electrostatic Discharge Voltage pins relative to GND | Human body model | XC3S50 | - | ±1500 | V |
| Other | - | ±2000 | V | |||
| Charged device model | - | ±500 | V | |||
| Machine model | - | ±200 | V | |||
| TJ | Junction temperature | - | 125 | |||
| TSOL | Soldering temperature | - | 220 | |||
| TSTG | Storage temperature | -65 | 150 | |||
XC3S1000 Features
• Low-cost, high-performance logic solution for high-volume, consumer-oriented applications
- Densities up to 74,880 logic cells
• SelectIO™ signaling
- Up to 784 I/O pins
- 622 Mb/s data transfer rate per I/O
- 18 single-ended signal standards
- 8 differential I/O standards including LVDS, RSDS
- Termination by Digitally Controlled Impedance
- Signal swing ranging from 1.14V to 3.45V
- Double Data Rate (DDR) support
- DDR, DDR2 SDRAM support up to 333 Mbps
• Logic resources
- Abundant logic cells with shift register capability
- Wide, fast multiplexers
- Fast look-ahead carry logic
- Dedicated 18 x 18 multipliers
- JTAG logic compatible with IEEE 1149.1/1532
• SelectRAM™ hierarchical memory
- Up to 1,872 Kbits of total block RAM
- Up to 520 Kbits of total distributed RAM
• Digital Clock Manager (up to four DCMs)
- Clock skew elimination
- Frequency synthesis
- High resolution phase shifting
• Eight global clock lines and abundant routing
• Fully supported by Xilinx ISE development system
- Synthesis, mapping, placement and routing
• MicroBlaze™ processor, PCI, and other cores
• Pb-free packaging options
• Low-power Spartan-3L Family and Automotive Spartan-3 XA Family variants
- Densities up to 74,880 logic cells
• SelectIO™ signaling
- Up to 784 I/O pins
- 622 Mb/s data transfer rate per I/O
- 18 single-ended signal standards
- 8 differential I/O standards including LVDS, RSDS
- Termination by Digitally Controlled Impedance
- Signal swing ranging from 1.14V to 3.45V
- Double Data Rate (DDR) support
- DDR, DDR2 SDRAM support up to 333 Mbps
• Logic resources
- Abundant logic cells with shift register capability
- Wide, fast multiplexers
- Fast look-ahead carry logic
- Dedicated 18 x 18 multipliers
- JTAG logic compatible with IEEE 1149.1/1532
• SelectRAM™ hierarchical memory
- Up to 1,872 Kbits of total block RAM
- Up to 520 Kbits of total distributed RAM
• Digital Clock Manager (up to four DCMs)
- Clock skew elimination
- Frequency synthesis
- High resolution phase shifting
• Eight global clock lines and abundant routing
• Fully supported by Xilinx ISE development system
- Synthesis, mapping, placement and routing
• MicroBlaze™ processor, PCI, and other cores
• Pb-free packaging options
• Low-power Spartan-3L Family and Automotive Spartan-3 XA Family variants
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