USD700, USD735, USD735C Selling Leads, Datasheet
MFG:N/A Package Cooled:9800 D/C:TO
USD700, USD735, USD735C Datasheet download
Part Number: USD700
MFG: N/A
Package Cooled: 9800
D/C: TO
USD700, USD735, USD735C
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Info of USD700
Info of USD735
Info of USD735C
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About USD700
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Datasheet: USD700
File Size: 156531 KB
Manufacturer: ATMEL [ATMEL Corporation]
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About USD735
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Datasheet: USD735
File Size: 86519 KB
Manufacturer: MICROSEMI [Microsemi Corporation]
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About USD735C
PDF/DataSheet Download
Datasheet: USD735C
File Size: 86828 KB
Manufacturer: MICROSEMI [Microsemi Corporation]
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USD700 General Description
The UA1 series of ULCs is well suited for conversion of large sized CPLDs andFPGAs. We can support within one ULC from 18 Kbits to 390 Kbits DPRAM and from46 Kgates to 780 Kgates. Typically, ULC die size is 50% smaller than the equivalentFPGA die size. DPRAM blocks are compatible with Xilinx or Altera FPGA blocks.Devices are implemented in highperformance CMOS technology with 0.35µm(drawn) channel lengths, and are capable of supporting flipflop toggle rates of 200MHz at 3.3V and 180 MHz at 2.5V, and input to output delays as fast as 150ps at 3.3V.
The architecture of the UA1 series allows for efficient conversion of many PLD archi-tecture and FPGA device types with higher IO count. A compact RAM cell, along withthe large number of available gates allows the implementation of RAM in FPGA archi-tectures that support this feature, as well as JTAG boundaryscan and scanpathtesting.
Conversion to the UA1 series of ULC can provide a significant reduction in operatingpower when compared to the original PLD or FPGA. This is especially true when com-pared to many PLD and CPLD architecture devices, which typically consume 100mAor more even when not being clocked. The UA1 series has a very low standby con-sumption of 0.3nA/gate typically commercial temperature, which would yield astandby current of 42µA on a 144,000 gates design.
Operating consumption is a strictfunction of clock frequency, which typically results in a power reduction of 50% to 90%depending on the device being compared.
USD700 Maximum Ratings
Operating Temperature
Commercial.............................................0° to 70°C
Industrial.............................................-40° to 85°C
Max Supply Core Voltage (VDD)..........................3.6V
Max Supply Periphery Voltage (VDD5).................3.6V
Input Voltage (VIN)VDD....................................+0.5V
5V Tolerant/Compliant VDD5.............................+0.5V
Storage Temperature........................-65° to 150°C
Operating Ambient Temperature.......-55° to 125°C
Commercial.............................................0° to 70°C
Industrial.............................................-40° to 85°C
Max Supply Core Voltage (VDD)..........................3.6V
Max Supply Periphery Voltage (VDD5).................3.6V
Input Voltage (VIN)VDD....................................+0.5V
5V Tolerant/Compliant VDD5.............................+0.5V
Storage Temperature........................-65° to 150°C
Operating Ambient Temperature.......-55° to 125°C
USD700 Features
• High performance ULC family suitable for large-sized CPLDs and FPGAs
• From 46K gates up to 780K gates supported
• From 18 Kbit to 390 Kbit DPRAM
• 100% compatible with Xilinx or Altera
• Pin counts to over 976 pins
• Any pinout matched due to limited number of dedicated pads
• Full range of packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, BGA, PGA/PPGA
• Low quiescent current: 0.3 nA/gate
• Available in commercial and industrial grades
• 0.35 µm Drawn CMOS, 3 and 4 Metal Layers
• Library Optimised for Synthesis, Floor Plan & Automatic Test PatternGeneration (ATPG)
• High Speed Performances: 150 ps Typical Gate Delay @3.3V Typical 600 MHz Toggle Frequency @3.3V Typical 360 MHz Toggle Frequency @2.5V
• High System Frequency Skew Control: Clock Tree Synthesis Software
• Low Power Consumption:0.25 µW/Gate/ MHz @3.3V0.18 µW/Gate/ MHz @2.5V
• Power on Reset
• Standard 2, 4, 6, 8,10, 12 and 18mA I/Os
• CMOS/TTL/PCI Interface
• ESD (2 kV) and Latch-up Protected I/O
• High Noise & EMC Immunity: I/O with Slew Rate Control Internal Decoupling Signal Filtering between Periphery & Core
• Thick oxide matrices allowing 5V tolerance
• From 46K gates up to 780K gates supported
• From 18 Kbit to 390 Kbit DPRAM
• 100% compatible with Xilinx or Altera
• Pin counts to over 976 pins
• Any pinout matched due to limited number of dedicated pads
• Full range of packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, BGA, PGA/PPGA
• Low quiescent current: 0.3 nA/gate
• Available in commercial and industrial grades
• 0.35 µm Drawn CMOS, 3 and 4 Metal Layers
• Library Optimised for Synthesis, Floor Plan & Automatic Test PatternGeneration (ATPG)
• High Speed Performances: 150 ps Typical Gate Delay @3.3V Typical 600 MHz Toggle Frequency @3.3V Typical 360 MHz Toggle Frequency @2.5V
• High System Frequency Skew Control: Clock Tree Synthesis Software
• Low Power Consumption:0.25 µW/Gate/ MHz @3.3V0.18 µW/Gate/ MHz @2.5V
• Power on Reset
• Standard 2, 4, 6, 8,10, 12 and 18mA I/Os
• CMOS/TTL/PCI Interface
• ESD (2 kV) and Latch-up Protected I/O
• High Noise & EMC Immunity: I/O with Slew Rate Control Internal Decoupling Signal Filtering between Periphery & Core
• Thick oxide matrices allowing 5V tolerance
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