TC35256FT-55U, TC3525CPE, TC35273 Selling Leads, Datasheet
MFG:1760 Package Cooled:DIP D/C:TOSHIBA
TC35256FT-55U, TC3525CPE, TC35273 Datasheet download
Part Number: TC35256FT-55U
MFG: 1760
Package Cooled: DIP
D/C: TOSHIBA
TC35256FT-55U, TC3525CPE, TC35273
- Table of contents:
Info of TC35256FT-55U
Info of TC3525CPE
Info of TC35273
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About TC3000
PDF/DataSheet Download
Datasheet: TC3000
File Size: 43665 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
About TC3000
PDF/DataSheet Download
Datasheet: TC3000
File Size: 43665 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
About TC35273
PDF/DataSheet Download
Datasheet: TC35273
File Size: 247399 KB
Manufacturer: TOSHIBA [Toshiba Semiconductor]
Download : Click here to Download
TC35273 Features
· TC35273 is an MPEG-4 audiovisual codec LSI which supports 3GPP 3G-324M video telephony system. MPEG-4
video codec with QCIF (176x144 pixel) at 15 frames/s, AMR (Adaptive Multi Rate) speech codec, and ITU-T
H.223 are executed concurrently at around 70MHz clock rate.
· Three signal processing units, an MPEG-4 video codec, a speech codec / audio decoder, and a multiplex
/ demultiplex unit, are integrated on a single chip.
· A 12-Mbit embedded DRAM is integrated as a shared memory for the three signal processing units. The
embedded DRAM helps to reduce power consumption without performance degradation.
· Each signal processing unit consists of a 16-bit RISC processor and dedicated hardware accelerators so
as to bring programmability, high performance and low power consumption.
·Firmware programs for the RISCs are downloaded into the embedded DRAM before starting operation.
Various applications are performed by choosing an appropriate firmware.
·General host interface are adopted in order to support various host CPU.
·2.5x to 6x of PLL is integrated on the chip for easy system integration.
video codec with QCIF (176x144 pixel) at 15 frames/s, AMR (Adaptive Multi Rate) speech codec, and ITU-T
H.223 are executed concurrently at around 70MHz clock rate.
· Three signal processing units, an MPEG-4 video codec, a speech codec / audio decoder, and a multiplex
/ demultiplex unit, are integrated on a single chip.
· A 12-Mbit embedded DRAM is integrated as a shared memory for the three signal processing units. The
embedded DRAM helps to reduce power consumption without performance degradation.
· Each signal processing unit consists of a 16-bit RISC processor and dedicated hardware accelerators so
as to bring programmability, high performance and low power consumption.
·Firmware programs for the RISCs are downloaded into the embedded DRAM before starting operation.
Various applications are performed by choosing an appropriate firmware.
·General host interface are adopted in order to support various host CPU.
·2.5x to 6x of PLL is integrated on the chip for easy system integration.
TC35273 Connection Diagram
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