SST49LF020, SST49LF020A, SST49LF020A-33-4C-NH 2M Selling Leads, Datasheet
MFG:SST Package Cooled:06+
SST49LF020, SST49LF020A, SST49LF020A-33-4C-NH 2M Datasheet download
Part Number: SST49LF020
MFG: SST
Package Cooled: 06+
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SST49LF020, SST49LF020A, SST49LF020A-33-4C-NH 2M
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Info of SST49LF020
Info of SST49LF020A
Info of SST49LF020A-33-4C-NH 2M
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About SST49LF020
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Datasheet: SST49LF020
File Size: 475687 KB
Manufacturer: SST [Silicon Storage Technology, Inc]
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About SST49LF020A
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Datasheet: SST49LF020A
File Size: 454017 KB
Manufacturer: SST
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About SST
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Datasheet: SST
File Size: 83114 KB
Manufacturer:
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SST49LF020 General Description
The SST49LF020 flash memory device is designed to interface with the LPC bus for PC and Internet Applicance
applications. It provides protection for the storage and update of code and data in addition to adding system design flexibility through five General Purpose Inputs (GPI). The SST49LF020 is in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC Mode for In-System programming
and Parallel Programming (PP) Mode for fast factory programming.
The SST49LF020 flash memory device is manufactured with SST's proprietary, high performance SuperFlash
Technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability
compared with alternate approaches. The SST49LF020 device significantly improves performance and reliability, while lowering power consumption. The SST49LF020 device writes (Program or Erase) with a single 3.0-3.6V power supply. It uses less energy during Erase and Program than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, current and time of application. Since for any give voltage range, the SuperFlash technology usesless current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST49LF020 product provides a maximum
Byte-Program time of 20µsec. The entire memory can be erased and programmed byte-by-byte typically in 4 seconds,
when using status detection features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. The SuperFlash technology provides fixed Erase and Program time, independent of the number of Erase/Program cycles that have performed. Therefore the system software or hardware does not have to be calibrated or correlated to the cumulative number of Erase/Program cycles as is necessary with alternative flash memory technologies, whose Erase and Program time increase with accumulated Erase/Program cycles.
To protect against inadvertent write, the SST49LF020 device has on-chip hardware and software data (SDP)
protection schemes. It is offered with a typical endurance of 100,000 cycles. Data retention is rated at greater than
100 years.
applications. It provides protection for the storage and update of code and data in addition to adding system design flexibility through five General Purpose Inputs (GPI). The SST49LF020 is in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC Mode for In-System programming
and Parallel Programming (PP) Mode for fast factory programming.
The SST49LF020 flash memory device is manufactured with SST's proprietary, high performance SuperFlash
Technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability
compared with alternate approaches. The SST49LF020 device significantly improves performance and reliability, while lowering power consumption. The SST49LF020 device writes (Program or Erase) with a single 3.0-3.6V power supply. It uses less energy during Erase and Program than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, current and time of application. Since for any give voltage range, the SuperFlash technology usesless current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST49LF020 product provides a maximum
Byte-Program time of 20µsec. The entire memory can be erased and programmed byte-by-byte typically in 4 seconds,
when using status detection features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. The SuperFlash technology provides fixed Erase and Program time, independent of the number of Erase/Program cycles that have performed. Therefore the system software or hardware does not have to be calibrated or correlated to the cumulative number of Erase/Program cycles as is necessary with alternative flash memory technologies, whose Erase and Program time increase with accumulated Erase/Program cycles.
To protect against inadvertent write, the SST49LF020 device has on-chip hardware and software data (SDP)
protection schemes. It is offered with a typical endurance of 100,000 cycles. Data retention is rated at greater than
100 years.
SST49LF020 Features
• Standard LPC Interface
Conforms to Intel LPC Interface Specification 1.0
• Organized as 256K x8
• Flexible Erase Capability
Uniform 4 KByte sectors
Uniform 16 KByte overlay blocks
16 KBytes Top boot block protection
Chip-Erase for PP Mode
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
• Low Power Consumption
Active Read Current: 10 mA (typical)
Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
Sector-Erase Time: 18 ms (typical)
Block-Erase Time: 18 ms (typical)
Chip-Erase Time: 70 ms (typical)
Byte-Program Time: 14 µs (typical)
Chip Rewrite Time: 4 seconds (typical)
Single-pulse Program or Erase
Internal timing generation
• Two Operational Modes
Low Pin Count (LPC) Interface mode for
in-system operation
Parallel Programming (PP) Mode for fast production
programming
• LPC Interface Mode
5-signal communication interface supporting
byte Read and Write
33 MHz clock frequency operation
WP# and TBL# pins provide hardware write protect
for entire chip and/or top boot block
Standard SDP Command Set
Data# Polling and Toggle Bit for
End-of-Write detection
5 GPI pins for system design flexibility
• Parallel Programming (PP) Mode
11 pin multiplexed address and
8 pin data I/O interface
Supports fast In-System or PROM programming
for manufacturing
• CMOS I/O Compatibility
• Packages Available
32-lead PLCC
32-lead TSOP (8mm x 14mm)
Conforms to Intel LPC Interface Specification 1.0
• Organized as 256K x8
• Flexible Erase Capability
Uniform 4 KByte sectors
Uniform 16 KByte overlay blocks
16 KBytes Top boot block protection
Chip-Erase for PP Mode
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
• Low Power Consumption
Active Read Current: 10 mA (typical)
Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
Sector-Erase Time: 18 ms (typical)
Block-Erase Time: 18 ms (typical)
Chip-Erase Time: 70 ms (typical)
Byte-Program Time: 14 µs (typical)
Chip Rewrite Time: 4 seconds (typical)
Single-pulse Program or Erase
Internal timing generation
• Two Operational Modes
Low Pin Count (LPC) Interface mode for
in-system operation
Parallel Programming (PP) Mode for fast production
programming
• LPC Interface Mode
5-signal communication interface supporting
byte Read and Write
33 MHz clock frequency operation
WP# and TBL# pins provide hardware write protect
for entire chip and/or top boot block
Standard SDP Command Set
Data# Polling and Toggle Bit for
End-of-Write detection
5 GPI pins for system design flexibility
• Parallel Programming (PP) Mode
11 pin multiplexed address and
8 pin data I/O interface
Supports fast In-System or PROM programming
for manufacturing
• CMOS I/O Compatibility
• Packages Available
32-lead PLCC
32-lead TSOP (8mm x 14mm)
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